ABSTRACT
This paper elaborates the high speed 8x8x8 3D-DCT/IDCT processor based on CORDIC algorithm for various DSP applications such as image and video processing coding with reduced size and cost of hardware. In this paper, CORDIC based 3D DCT/IDCT i.e. both forward and inverse computations required for transform has been presented. By using this algorithm image and video can be processed through the DCT/IDCT for the compression/decompression data. The number of CORDIC Computational requirement for N=8, N=16 3D DCT/IDCT for 8*8*8 is (N3+16)/12 has been compared with 2D-DCT algorithm. Based on this algorithm a new processor 3D-DCT/IDCT architecture is designed and simulated in Xilinx ISE 14.7 and FPGA implementation has been done in Altera Quartus cyclone II (DE2 board).
