ABSTRACT
Approximate computing has become ravishing approach for designing high performance and low energy consumption with limited loss in accuracy for many digital logic designs. Since there is a trade-off between speed/power with accuracy shown through previous research works. The demand of high speed and power efficiency as well as the feature of error tolerant applications has driven the development of approximate arithmetic circuits. The most important arithmetic modules in a processor are adder and multipliers to determine the performance for many computing tasks in today’s digital systems. A comparative study of efficient algorithm and architecture for various approximate multipliers are presented in this survey. Approximate multiplier reduces the transistor count, power consumption, delay and it provides high speed output. The result shows that the proposed Approximate multiplier design accomplish significant reductions in power dissipation, delay and transistor count compared to an exact accurate multiplier design with small loss in accuracy. Comparison of extensive simulation results are shown for approximate multiplier. An application in image processing is performed, where peak signal to noise ratio of the image is analyzed. The image quality of the approximate multiplier shows satisfactory result compared to an accurate multiplier.
