ABSTRACT
With the desire to improve performance of the HEVC’s De-blocking Filter, a new filtering order is proposed. This method maximally supports for parallel processing by dissolving the data dependency between the adjacent filtering operations. This order allows handling the horizontal edges and vertical edges at the same time. In this paper, we implement the HEVC De-blocking Filter architecture based on the new filtering order in a Xilinx Virtex 7 FPGA. This design has maximum clock frequency 113MHz, provide throughput up to 38 Gbps.
