ABSTRACT
Digital Signal processing became an application to create high speed data processing systems like 3D rendering, 4G mobile internet, etc., we need best processors with high performance data path units and there is a growing need for research on alternative methods for signal processing hardware implementation. In most systems using digital signal processing Multiply-Accumulate (MAC) is one of the main functions. The performance of the whole system depends on the performance of the MAC units in place. Regardless of that these days’ real time signal processing systems require high throughput and high performance MAC units. A MAC unit is simply one of the main units in all Digital Signal Processors which performs the multiplication of two numbers of any radix and accumulates the by-products in order. In this paper, a floating point multiply and accumulate unit is designed using ancient mathematics that reduces the number of partial products to be added as well as increases the speed of accumulation of partial products by reducing the number of stages of partial products that needs to be added thereby making it a high performance unit. The output of this unit is simulated using simulation software ModelSim SE plus 6.2C and the language used is VHDL.
