ABSTRACT
when we require developing digital integrated circuits, then we are facing many challenges like the way of greater energy consumption. The mixture of minor procedure geometries, greater functional integration and higher clock speed shave contributed to important enhanced in power density, so there are many methods which can be utilized to decrease leakage power in the efficient way. In this paper we proposed a newest method known as LECTOR for designing CMOS Ring oscillator that significantly cuts down the leakage current without increasing the dynamic power dissipation. In this work we calculated leakage power and leakage current. We found that after using this novel technique, circuit leakage parameters reduces drastically. We used SPICE tool for simulation with 45nm technology mode. 0.7v and 1.0v supply voltage is used in this work.
