ABSTRACT
Power optimization is a very crucial issue in low voltage applications. This paper presents a design of D-Flip flop circuit using AVL techniques for low power operation. It reduces the value of total power dissipation of applying the adaptive voltage level at ground (AVLG) technology in which the ground potential is raised and adaptive voltage level of supply (AVLS) in which supply potential is increased. The main aim of the design is to investigate the power dissipation for D-Flip flop for the proposed design style. The simulation results show the there is a significant reduction in power consumption of this proposed cell with the AVL technique. The AVLS technique has less power dissipation 1.13 nwatts compared to AVLG technique 2.25 nwatts. The circuit is designed using H-Spice 130nm technology.
