ABSTR
This paper proposes an improved Two Phase Clocked Adiabatic Static CMOS logic (2PASCL) circuit. The proposed circuit is based on energy recovery adiabatic principle which consumes less power. The number of transistor required in proposed circuit is same as that of reported 2PASCL. Various combination circuits such as inverter, NAND, NOR, XOR has been designed using both the logic style. A two phase complementary sinusoidal power clock has used with different frequency. Detailed power analysis, delay analysis, Power Delay product analysis between proposed 2PASCL, Reported 2PASCL and CMOS logic has been performed over a frequency range from 20Mhz to 100 Mhz. In the proposed inverter and combinations circuits the power efficiency has been improved to almost 18% compared to CMOS and reported 2PASCL logic. Also it has been observed that if input signal frequency is equal or doubled the clock frequency then the proposed circuit gives best performance. The 2PASCL technology finds application in low power digital devices.
